Fail-safe time delay relay



Haiku-906.

lzdvew 3y u A. u H15 wma/Vif Oct. 22, 1968 l 5 uw Ill l I I. www WN wd4mm NN mw KQ United States Patent Ofic-ce Patented Oct. 22, 19683,407,340 FAIL-SAFE TIME DELAY RELAY Andrew Hufnagel, Crescent Hills,Pa., assignory to Westinghouse Air Brake Company, Swissvale, Pa., acorporation of Pennsylvania Filed June 14, 1966, Ser. No. 557,512 18Claims. (Cl. 317-142) This invention relates to a solid state timeelement relay.

Morev specifically, this invention relates to a fail-safe solid statetime element relay which is immune to relay pick-up due to earlytriggering induced by circuit component failure or induced voltagetransients. The time delay relay of the invention is capable of a broadrange of adjustable time intervals followed by a quick relay pickup atthe end of the time intervals. In addition there is absolute certaintythat release of the relay will occur in a vitally 4safe manner.

The time element relay of this invention finds particular application inthe railway signaling field and it should be recognized at the outsetthat, while the invention may have application in other fields, theinvention to be described advances the time delay relay art in therailway signaling area of technology. Throughout the description of theinvention it should be kept in mind that fail-safe operation of a timedelay relay in any rapid mass transit eld is not just a g'oal to besought but a goal that must be attained in the unequivocal sense. Nolonger are vehicles of mass transit pursuing headway and speeds measuredin units of minutes and units of velocity between zero vand 60 miles perhour, but the mass transit systems of today and years to come willmeasure headway between vehicles in seconds and speed of the vehicles inhundreds of miles per hour. It is against this background of rapidlychanging and advancing technology that the invention to be describedgains true perspective and the need for vitaL fail-safe operation.

Prior art time element relays for railway signaling have incorporated agear train, driven by a stepping mechanism or a governor controlleddirect current motor, which gradually closed the contacts. In this typeof system to ensure vit-al, fail-safe full pickup time it was necessaryto provide check contacts, which would close only with the relaymechanism fully released and this would occur in connection with relatedexternal circuitry. These relays have always required periodic oilingand adjustment and, of course, are subject to wear.

More recently, time delay relays employing solid state techniques haveentered the art for use in other applications where vital, fail-safeoperation is not critical. Typical of these solid state time elementrelays is the relay and related circuitry depicted in the GeneralElectric Transistor Manual, 6th Edition, page 198, which has aunijunction transistor as its active element. This unijunctiontransistor per the Manual noted above may have substituted therefor asilicon controlled switch and in place of the silicon controlled switchthere may be substituted a pair of transistors. These substitutions areof course those which may be deemed to be obvious expedients. It shouldbe recognized that these obvious substitutions do not provide a vital,fail-safe relay. In the general version of the time delay relay notedabove a capacitor is charged through a high value of resistance to somespecific proportion of full charge, at which time a semiconductortrigger device discharges the capacitor through a small relay, whichpicks up and is thereafter held -up over a front contact. In thistypical solid state time delay relay as well as the recent prior art itwill be observed that in case of reverse leakage at the transistor ortransistors, as the case may be, the pickup time of the time delay relaycould be greatly shortened due to the capacitor receiving additionalcharging current through the transistor. Furthermore, if a high supplyvoltage were to suddenly appear and the transistor became shorted, therelay would pick up with no time delay at all. This would result intragic consequence in a mass transit system of the type previouslyoutlined. In addition, at the higher supply voltage, a momentaryinterruption in the supply will cause a loss of reference voltage at thetransistor, causing it to trigger early, with enough stored energy fromthe capacitor to pick up the relay. All of these just noted problems arecompletely obviated by the invention to be described hereafter.

It is therefore an object of this invention to provide a solid statefail-safe relay circuit that is immune to early triggering and relaypickup.

Another object of this invention is to provide a solid state time delayrelay circuit in which there is provided a standby reference voltagesource to thereby instantly prevent early triggering and `relay pickupin the event that there is a momentary interruption of the supplyvoltage.

Yet another object of this invention is to provide a relay time delaycircuit with the highly desirable capability of withstanding wide rangesin power input, induced voltage transients and shorted active elementswhile maintaining a reasonable control over the time delay periodinvolved.

Another object of this invention is to provide a relay time delaycircuit which has its fail-safe qualities enhanced by a novel multiplecapacitor timing element.

In the attainment of the foregoing objects this invention embraces theneed for a solid state time delay relay which will not pick up due toearly triggering brought about by externally and internally inducedtransient vo1tage signals while simultaneously affording the capacity toprovide adjustable time intervals followed by quick relay pickup at theend of the intervals.

The time delay relay includes in combination an externally controlleddirect current voltage source which supplies power to a solid staterelay energization control circuit, which circuit includes a first andsecond transistor each having an emitter, a base and a collector.Interposed between the direct current power source and the solid staterelay energization control means is an adjustable time delay voltagestorage circuit which is mutually electrically connected to both thedirect current power source and the solid state relay energizationcontrol circuit.

A safety voltage storage circuit is electrically connected to both thedirect current voltage source and the adjustable time delay voltagestorage circuit. This safety voltage storage circuit provides astandbyreference voltage for the first and second transistors of thesolid state relay energization control circuit. The relay to be actuatedand a reference voltage control circuit are both electrically connectedto the solid state relay energization control circuit. The emitter ofthe first transistor is electrically connected to the time delay voltagestorage circuit and the base of the [first transistor is mutuallyelectrically connected to the collector of the second transistor and thereference voltage control circuit. The collector of the first transistoris electrically connected to the base of the second transistor while theemitter of the second transistor is electrically connected to the coilof the relay.

The first transistor will become conducting when the voltage level inthe adjustable time delay voltage storage circuit exceeds the referencevoltage level in the reference voltage control circuit. The secondtransistor is rendered conducting upon the commencement of conduction ofthe first transistor. The final basic component of the system is abypass circuit for the solid state relay energization control circuitand the reference voltage control circuit.

3 .Y This bypass circuit is electrically connected to the direct currentvoltage source and controlled by the relay to provide a bypass circuitto maintain the relay energized.

Simultaneously With the conduction of the rst and second transistors theadjustable time delay voltage storage circuit delivers its stored energythrough the transistors to energize the relay and the reference voltageis brought to zero by the completion of the bypass circuit to the relay.This results in the relay being quickly picked up and maintained pickedup by the combined action of the stored voltage energy in the adjustabletime delay storage circuit and the bypass circuit.

Other objectives and advantages of the present system will becomeapparent from the ensuing description of illustrative embodimentsthereof, in the course of which reference'is had to the accompanyingdrawings.

FIG. l is a circuit embodying the invention.

FIG. 2 is a novel capacitor arrangement.

A description of the above embodiment will follow and then the novelfeatures of the invention will be presented in the appended claims.

Reference is now .made to FIG. l. In FIG. l there is depicted a circuitwhich provides the variable time delay sought by this invention. It willbe noted that there appear not only the basic components of thecircuitry set forth here but there are a number of blocks or boxes shownin dotted outline. Each of these blocks or boxes shown in dotted outlineis intended to include one or more of the various means to be referredto hereafter. It is hoped that this approach will aid in theunderstanding of what is intended to be included in the various meansrecited hereafter, and what is intended to be included within each ofthe various means as the description ensues. Furthermore, it is believedthat this approach will facilitate an understanding of the claims whichappear appended hereafter, and set forth the precise invention asclaimed.

Accordingly, there is present here a direct current voltage source 11.In this instance the direct current voltage source may be a 10, 12 or16-volt source and the delay for this system, as shown in this preferredembodiment, may range from 3 to 30 seconds and from 1/2 to 5 minutes induration. It will be appreciated that while these are suggested rangesof time delay, they may be varied to be longer or shorter dependent uponthe circuit parameters selected by those wishing to employ theinvention.

Accordingly, it is seen that there is a direct current voltage source 11which supplies the power to operate a relay 60, shown here in dottedoutline in the righthand portion of FIG. 1. This relay 60 and its coil61 is the principal component to be operated at the end of apredetermined time delay which has been designed into the system. And ashas been pointed out earlier, this relay 60 must receive its energy witha distinctive and sudden input in order that the relay 60 and its coil61 react quickly to the application of energy at the end of thepredetermined time delay involved. It will be seen that two electricalleads 12 and 14 emanate from the direct current voltage source 11. Theelectrical lead 12 has a portion thereof interrupted by the presence ofa switch which will control the application of the direct current energyto the various components in the circuit to be described. The electricalleads 12 and 14, to the extent that they are the same electrical leads,have portions thereof designated 12a through 12f and 14a through 14g,respectively. This has been done to further enhance the understanding ofthe theory of the circuit operation which will now ensue.

Serially connected to the input lead 12 is a resistor R1, which resistorR1 .limits the power input to the circuitry and has a value selected tomatch the nominal s-upply voltage. Connected across the electrical leads12a and 14 is a Zener diode D1 which limits the voltage which willappear across the electrical leads 12a and 14 to a pre- 4 determinedmaximum level. This Zener diode D1, which is incorporated in the dottedoutline portion of this ligure, has been designated a voltage limitingmeans 13 and this voltage limiting ymeans 13, which includes the Zenerdiode D1, provides the capacity to prevent the delivery of momentaryincreases in power to the remaining portions of the circuitry depictedto the right of the Zener diode D1. In other words, momentary increasesin power supply voltage from the direct current voltage source 11 willbe clipped off by the Zener diode D1. This increase which may arise maytrace its source to a sudden voltage pulse in the line wires when thedirect current voltage source and its related system is involved inrailway signaling. 'It goes without saying that any sudden voltageincrease will have its effectiveness controlled by the Zener diode D1 ofthe voltage limiting means 13.

Connected across the electrical leads 12b and 14a is a resistor R2 whichis enclosed in a dotted outline block which will be designated as theexcess voltage drainoff means, the precise function of which will bemade clear hereafter. The electrical leads 12b and 14a and theirextensions 12c and 14b convey the supply voltage to the capacitor C1connected by electrical leads 23 and 24 to the leads 12C and 14b. Thecapacitor C1 is shown enclosed in the dotted outline box 22 and will bereferred to hereafter as a safety voltage storage means 22. Adjacent tothe safety voltage storage means 22 there is a. box shown in dottedoutline and designated by the reference numeral 26. This will behereafter referred to as an adjustable time delay storage means. Thisadjustable time delay storage means includes a variable resistancepotentiometer connected electrically by lead 27 to the lead 12d. Thereis also a vresistor R5 in series with the variable potentiometerconnected thereby by electrical lead 28. The resistor R5 and itsfunction in the system will be explained hereafter. The resistor R5 isconnected electrically via the electrical lead 29 to a capacitor C2, aswell as by an electrical lead 31 to the emitter 35 of a transistor Q1.This transistor Q1 will be referred to hereafter as the lirsttransistor. The capacitor C2 is in turn connected to the electrical lead14C by lead 30. It will be appreciated that the electrical lead 14, aswell as 14a, b, c and d, is respectively electrically connected to aground depicted here at the bottom of the ligure. This ground is aconnection to a magnetic shielding 20 shown in dotted outline. Thismagnetic shielding 20 and its function will be eX- plained more fullyhereafter.

The adjustable time delay storage. means 26 is connected via electricallead 12e, a resistor R8, and lead 12j", to the reference voltage controlmeans 50, which reference voltage control means 50 is shown in dottedoutline. The reference voltage control means 50 includes a pair ofresistors R6 and R7. Interposed between the reference voltage controlmeans 50 and the adjustable time delay storage means 26 is a solid staterelay energization control means 25, which solid state relayenergization control means 25 has a pair of transistors Q1 and Q2. Theemitter 35 of first transistor Q1, as has been noted, is electricallyconnected via the lead 31 to the adjustable time delay voltage storagemeans 26. The base 36 of the transistor Q1 is connected by lead 34 to alead 33 which in turn is connected by lead 48 to the reference voltagecontrol means 50. The collector 37 of the transistor Q1 is electricallyconnected via the lead 38 to the base 45 of the second transistor Q2,while the collector 44 of the second transistor Q2 iselectrically-connected to the lead 33 which in turn is electricallyconnected to the lead 34 and the base 36 of the transistor Q1. Thecollector 37 of the first transistor Q1, as well as the base 45 of thesecond transistor Q2, is mutually electrically connected via the lead 38and the lead 39 to a resistor R9, and lea'd 41 to electrical lead 14ewhich is an extension, as has been noted, of the electrical lead 14;

Interposed in the circuitry between the adjustable time delay storagemeans 26 and the solid state relay energization control means 25 isaxsignal transient suppression means 55. This signal transientsuppression means 55, shown in dotted outline, includes a resistor R3and a diode D3 in series between the electrical leads 58 and 59 whichemanate from the leads 14d and 14e, respectively. Leads 58 and 59 areconnected to the opposite ends of the relay coil 61 of the relay 60shown in dotted outline. Directly beneath the relay `60 is a box shownin dotted outline which will be referred to hereafter as a bypass means66. This bypass means 66 includes a contact a which completes a circuitbetween the right-hand end of the relay coil 61 and the referencevoltage control means 50 over the electrical lead 63 which enters at thetop right-hand corner of the reference voltage control means 50. It willbe appreciated that when the relay 60 is energized it is intended thatthe` contact a be picked up and complete a circuit over the frontcontact a of this relay 60, and at this point the bypass means 66 willcomplete a circuit, as noted earlier, and there will be a circuitcompleted from the reference voltage control means 50 through the lead63, front contact a of the relay 60, lead 62, coil 61, lead 5,8, leads14d, 14e, 1417, 14a and 14 to the direct current voltage source tothereby provide a circuit which will maintain the relay 60 energized.

FIG. 2 depicts a multiple capacitor arrangement that may be utilized inplace of the capacitor C2 shown in IFIG. 1. This multiple capacitorarrangement plays a signicant role in the fail-safe qualities of thistime delay circuit. The capacitor C2 in FIG.2 is shown in dotted outlineand includes a plurality of capacitors, in this instance, sixcapacitors, electrically coupled in the manner shown. It will beappreciated that, for example, capacitor 51, which is typical of theremaining capacitors depicted, has four electrical connections present.The irst electrical connection is that at the point 56 where the onehalf of the capacitor51 is secured to the electrical lead 29. The otherhalf of the capacitor 51 is connected to electrical lead 30 at the point57. And in order to provide a failsafe environment there have beensoldered across all the leads depicted here two wires 53 and 54 whichare soldered, for example, at points 64 and 65 to either side of the`capacitor 51. It can therefore be appreciated that in the event a solderjoint fails at any one of these capacitors, .there would remain anadditional solder joint on that side of the capacitor` to the end thatwhile the entire group of capacitors might become open-circuited at lead29 or 30, there is little likelihood of losing one or two of the sixcapacitors.

Turning now to the operation of the circuit just described, when theswitch 10 is closed the direct current voltage source 11 will beconnected to the adjustable time delay circuitry and the following willoccur. Upon the closing of the switch the voltage level, which scontrolled as has been noted by the voltage limiting means 13, willtherefore appear across some of the remaining components depicted to therightrof the voltage limiting means 13. The direct current voltageselected for this particular design would be approximately 7.5 volts.The resistors R6 and R7, which form the reference voltage control means50, act as a voltage divider for the transistors Q1 and Q2. Theseresistors R6 and R7, which are much higher in resistance than theVresistor R8 and the resistance of the coil 61, provide a triggerreference voltage for the transistors Q1 and Q2 of the solid state relayenergization control means 25. The resistors R6 and R7 function as aconventional voltage divider which provides the reference voltage to beapplied to the base 3.6 of the first transistor Q1 via the leads 34, 33and 48.

Theadjustable time delay storage means 26, as has been noted, includes acapacitor C2. In this particular embodiment, while this capacitor C2 isshown as one capacitor it is to be understood that this capacitor C2 yisa multiple capacitor arrangement which is set forth in FIG. 2.

This capacitor C2 charges gradually through the time adjustment variableresistance potentiometer over the electrical leads 27, 28, resistor R5,lead 29, to the capacitor C2 which is connected via the lead 30 ltoground. Resistor R5 limits the minimum time adjustment for the timedelay function of the circuit while the variable resistancepotentiometer may be varied to control the time required to charge thecapacitor C2 and therefore provide the adjustable time delay for thetime Arelay circuitry being described.

The transistor Q1 of the solid state relay energization control means 25will conduct when the emitter 35 becomes more positive than the base 36.This will occur after the capacitor C2 in the adjustable time delaystorage means 26 has been charged to a point where the voltage presentin the capacitor C2 exceeds the reference voltage provided by thereference voltage control means 50 and its related resistors R6 and R7.In other words, when the emitter 35 of the transistor Q1 becomes morepositive than the base 36 of the transistor Q1, transistor Q1 willconduct and the capacitor C2, in a manner to be desribed hereafter,.will discharge through the lead 219, lead 31, to the transistor Q1. Thetransistor Q1, in this embodiment of the invention, is normallynonconducting until capacitor C2 has charged to a level which exceedsthe voltage reference level provided by the resistors R6 and R7 of thereference voltage control means 50. When transitsor Q1 conducts it willbias transistor Q2 into conduction. In other words, the base 45 of thetransistor Q2 will become more positive than its emitter 46.

With transistor Q2 conducting, transistor Q1 will be further biasedint-o conduction. This further biasing of transistor Q1 into conductionis a regenerative action and therefore drives both transistors Q1 and Q2into saturation, and they will remain triggered until the currentthrough them is reduced to some small value inherent in the transistorsselected. As has been noted, once the capacitor C2 of the adjustabletime delay storage means 26 has been charged to a level which exceedsthe reference voltage supplied by the reference voltage control means50, the capacitor C2 will discharge through elec trical leads 29, 31,transistor Q1, and transistor Q2 to leads 14j, 14e, 59, through relaycoil 61 of relay 60, lead 58, leads 14d, 30, to the capacitor C2,thereby causing the relay 60 to pick up due to energy from capacitor C2,and close the contact a of the bypass means 66 which therefore completesa circuit from the right-hand end of coil 61 over the lead 62, the frontcontact a of the relay 60, lead 63, to the lead 12f, where the lead 12jenters the reference voltage control means 50 This completed circuitjust noted `will hold the relay 60 picked 1p by the circuit justdescribed, due to energy from the direct current voltage source. Thiscompleted circuit causes the reference voltage at the 4junction of theresistors R6 and R7 to go to zero, and the transistors Q1 and Q2remainconductive due t-o a very small current which is above the cutoffcurrent of the transistors Q1 and Q2, which current passes through thevariable resistance potentiometer and the resistance R5 of theadjustable time delay storage means 26, and the transistors Q1, Q2 andthe leads 14f, 14e, 59, coil 16, lead 58, lead 14a', lead 14e` toground. It is therefore to be appreciated that the relay 60 ismaintained energized by the bypass curcuit which includes the bypassmeans 66 but there is an additional path in which a low level of currentis constantly flowing. That path includes the transistors Q1 and Q2 justnoted.

In the preferred embodiment the voltage drop in the transistors Q1 andQ2 at this point in the operation is about .4 of a volt, and the voltagedrop in the coil 61, due to the holding current, is about 2.7 volts.Accordingly, the capacitor C2 stabilizes at a charge of 2.7 volts plus.4 of a volt or 3.1 volts.

The resistor R2, which forms the heart of the excess voltage drainoffmeans 118, performsthe important function of providing a rapid drainoffof residual charges that appear on the capacitor C2 of the adjustabletime delay storage means 26. Since whether or not a circuit triggers thetransistors Q1 and Q2 it will be observed that any residual charges atthe capacitor C2 will drain off more rapidly through the resistor R2which, by design, is about 5K, to ground than through resistors R6 andR7 of the reference voltage control means which combined resistance isabout 2700K, to ground. In other words, there is a preferential paththrough the resistor R2 which provides the important function ofdraining off excess voltage which will appear on the capacitor C2 whichwhen fully charged discharges through the transistors Q1 and Q2 toenergize the relay 60 in a manner described earlier.

The capacitor C1 which is connected across the leads 12C and 14b via theleads 23 and 24 provides what is termed a safety voltage storagefunction and therefore the designation of this capacitor as a safetyvoltage storage means 22. The capacitor C1 of the safety voltage storagemeans 22 stores enough energy to prevent early triggering of thetransistors Q1 and Q2 due to loss of the reference voltage during anymomentary interruption of input power. In other words, the capacitor C1stores suicient energy to maintain the reference voltage at a level thatwill not permit the transistors Q1 and Q2 to fire when there appears amomentary interruption in power from the direct current voltage source11. The capacitor C1 of the safety voltage storage means 22 is alsoimportant from the standpoint that should there be an induced pulseimpressed in the line wires that supply the direct current voltagesource from the power supply and should this pulse be of a negativenature, this would cause a reduction in the reference voltage whichcould cause early triggering of the transistors Q1 and Q2 if the safetyvoltage storage means capacitor C1 were not present within the circuitryand did not have available the stored energy needed to maintain thisreference voltage. Again, it should be appreciated that this provides afeature of fail-safe operation which is of great importance to thesafety and the integrity of the time delay circuitry involved here.

When the direct current voltage source 11 and the circuits that supplythe power to the relay are opened, as when the switch is opened, thereference voltage which, as has been noted, is zero due to the bypasscircuitry around the reference voltage control means 50, the capacitorC2 discharges completely through transistors Q1 and Q2, the relay coil61 causing the relay 60 to release. The resistor R3 of the signaltransient suppression means 55 is important for the following reasons,If the resistor R3 were shunted so that it were out of the circuit, thetransistors Q1 and Q2 would cease to conduct at some low value ofcurrent. This would leave a small positive charge on the capacitor C2.Accordingly, if resistor R3 were removed, i.e. R3 were opened, collapseof the electromagnetic ield of the relay coil 61 would prolong thedischarge of capacitor C2 of the time delay storage means 26 until itassumed a small negative charge. This, of course, would affect the timeperiod of the next delay which would be bad. Accordingly, it can be seenthat by adjusting the value of the resistor R3 in the signal transientvsuppression means 55, the capacitor C2 can be left with exactly a zerocharge. The signal transient suppression means 55 includes a diode D3.This diode D3 is important for it prevents current from being shuntedaround the relay coil 61, which would tend to prevent the relay frompicking up, and also prevent the early triggering of the transistors Q1and Q2 due to an induced signal which may appear within the system uponthe release of an adjacent relay. While, for purposes of example, thissudden transient voltage just noted might be induced by the release ofan adjacent relay, it should be recognized that this suddenly inducedvoltage spike might come from any source externally of the relay herebeing described.

If the resistance R3 and the diode D3 were not present,

a voltage spike induced in the coil 61 of the relay 60 could add to thevoltage present on the capacitor C2 to produce a total voltage exceedingthe reference voltage which of course Iwould cause the transistors Q1and Q2 to be triggered which would result in the premature pickup of therelay which of course must never occur in this type of failsafeenvironment.

The capacitor C3, which is connected across the emitter 35 and the base36 of the transistor Q1 by the leads 32 and 33, functions as a buffer tothe transistor Q1 should there be an induced voltage spike which somehowreaches this tirst transistor Q1. The capacitance of the capacitor C3cooperates with a magnetic shield 20, referred to earlier, to protectthe transistor Q1 from such a voltage spike. Accordingly, the capacitorC3 prevents the early triggering of the transistor Q1 due toinstantaneous voltages at the transistor Q1, magnetically orelectrostatically induced which could cause a sudden variation in thereference voltage which would, of course, possibly cause transistor Q1to be triggered into conduction presenting the premature pickup of therelay which at all cost must be avoided.

The resistor R8, which is in the circuit between the electrical leads12e and 12j, limits the holding current which will appear in the bypasscircuit which includes the contact a of the relay 60, and this resistorR8 is selected merely to provide some nominal level of holding currentin the coil 61 of the relay 60.

The resistor R9 electrically connected via the leads y39 and 41 to theleads 38 and 14e, respectively, is needed to stabilize the bias on thetransistor Q2 to prevent leakage from the transistor Q1 from triggeringtransistors Q1 and Q2 early due to some high ambient temperatures. Theinclusion of this resistor R9 is a standard technique involved toobviate this possible early triggering due to elevated ambienttemperatures experienced by the system.

It will therefore be appreciated that the circuitry just described setsforth an embodiment of a time delay relay that is inherently safe onrelease and Iwhich can operate contacts quickly at the end of the timedelay involved rather than gradually. The basic safety feature is thatin the event of early triggering the relay will not pick up becausethere is not enough stored energy in the timing capacitors of theadjustable time delay storage means 26.

Obviously, certain modifications and variations of the invention ashereinbefore set forth may be made without departing from the spirit andscope thereof, and therefore only such limitations should be imposed asare indicated in the appended claims.

Having thus described my invention, what I claim is:

1. A fail-safe solid state time element relay which is immune to relaypickup due to early triggering, said time delay relay capable ofadjustable time intervals followed by quick relay pickup at the end ofsaid time intervals, said time element relay having in combination:

(l) an externally controlled direct current voltage source,

(2) solid state relay energization control means,

(3) a predetermined time delay voltage storage means electricallyconnected to said solid state relay energization control means,

(4) a safety voltage storage meanselectrically connected between saiddirect current voltage ,source and said predetermined time delay voltagestorage means, l

said voltage storage means storing energy from said direct currentvoltage source toA thereby provide a standby reference voltage to saidsolid state relay energization control means.

(5) an excess voltage drainoff means for' said lpr'edetermined timedelay voltage storage means electrically connected to said predeterminedtime delay voltage storage means,

(6) reference voltage control means electrically" connected to saidsolid state relay energization control means,

9 (7) a relay electrically connected to said solid state relayenergization control means, (8) a bypass means for said solid staterelay energization control means and said reference voltage controlmeans,

said `bypass means electrically connected `to said direct currentvoltage source and controlled by said relay to provide a bypass circuitto maintain said relay energized. 2. The fail-safe solid state timeelement relay of claim 1 wherein said solid state relay energizationcontrol means includes a first and second transistor each having anemitter, a base and a collector,

said emitter of said first transistor electrically connected to saidtime delay voltage storage means, said base of said first transistormutually electrically connected to said collector of said secondtransistor and said reference voltage control means, said collector ofsaid first transistor electrically connected to said base of said secondtransistor while said emitter of said second transistor is electricallyconnected to said relay, said first transistor becomes conducting whenthe voltage level in said predetermined time delay voltage storage meansexceeds the reference voltage level in said reference voltage controlmeans, said second transistor is rendered conducting upon thecommencement of said first transistor conduction, simultaneously withthe conduction of said first and second transistors said time delayvoltage storage means delivers its stored voltage energy through saidtransistors to energize said relay and said reference voltage is broughtto zero by the completion of said bypass circuit through said bypassmeans to said relay, whereby said relay is quickly picked up andmaintained picked up by the combined action of said stored voltage insaid predetermined time delay voltage storage means and said circuitthrough said bypass means. 3. The fail-safe solid state time elementrelay of claim 2 wherein said predetermined time delay storage meansincludes a series circuit which includes a variable resistance, a fixedresistance and a multiple capacitor means;

said multiple capacitor means charges gradually through said variableresistance and said lixed resistance which respectively provide a timeadjustment function and a minimum time adjustment for said time elementrelay. 4. The fail-safe solid state time element relay of claim 3wherein said multiple capacitor means includes a plurality of capacitorselectrically connected in parallel,

each capacitor having a pair of leads, said plurality of electricallyconnected parallel capacitors having an additional parallel pair ofelectrical connections across all of said capacitor leads, one said pairof additional electrical connections positioned on either side of saidplurality of capacitors and in electrical contact with said pairs ofelectrical leads to thereby provide a fail-safe capacitor arrangementimmune from the effects of possible failure of said parallel electricalconnection. 5. The fail-safe solid state time element relay of claim 4wherein said safety voltage storage means includes a capacitor whichstores enough energy to prevent early triggering due to loss of saidreference voltage during any momentary interruption of input power fromsaid direct current voltage source or the appearance in the directcurrent voltage source of an externally induced signal of negativenature.

6. The fail-safe solid state time element relay of claim 5 wherein saidexcess voltage drainol means includes a resistive element having aresistive value which is less than the total resistive value of saidreference voltage control means, said excess voltage drainol meansthere- 1.10 by providing arapid drainof of residual charges on saidmultiple capacitor means whether or not said solid state relayenergization means is triggered into conduction.

7. The fail-safe solid state time element relay of claim 6 wherein saidrelay includes transient signal suppression means to prevent relayenergizing current from bypassing the coil of said relay andsimultaneously. preventing early energization of said relay due toexternally induced transient voltage signals which would momentarilyincrease the voltage att said multiple capacitor means which would produce an early triggering of said solid state relay energlzation means.

8. The fail-safe sol-icl state time element relay of claim 7 whereinsaid transient signal suppression means also prevents early energizationof said relay due to externally induced transient voltage signals whichwould momentarily reduce said reference voltage in said referencevoltage means which would produce an early triggering of said solidstate relay energization means.

9. The fail-safe solid state time element relay of claim 8 whichincludes a voltage :limiting means electrically connected to said directcurrent voltage source and said predetermined time delay storage means,

said voltage limiting means clipping ofi excess voltage transients whichmay be impressed upon the direct current voltage source.

10. A fail-safe solid state time element relay which is immune to relaypickup due to early triggering brought about by externally andinternally induced transient voltage signals, said time delay relaycapable of adjustable time intervals followed by quick relay pickup atthe end of said time intervals, said time element relay havingincombination, v.

(l) an externally controlled direct current voltage source,

(2) solid state relay energization control means which includes a firstand a second transistor each having anemitter, a base and a collector, l

(3) a predetermined time delay voltage storage means electricallyconnected to said solid state relay energization control means,

(4) a safety voltage storage means electrically connected between saiddirect current voltage source and said predetermined time delay voltagestorage means,

said voltage storage means storing energy from said direct currentvoltage source to thereby provide a standby reference voltage to saidfirst and second transistors of said solid state relay energizationcontrol means,

(5) reference voltage control means electrically connected to said solidstate relay energization control means,

(6) a relay electrically connected to said solid state relayenergization control means,

said emitter of said first transistor electrically connected to saidtime delay voltage storage means, said base of said first transistormutually electrically connected to said collector of said secondtransistor and said reference voltage control means, said collector ofsaid first transistor electrically connected to said base of said secondtransistor while said emitter of said second transistor is electricallyconnected to said relay, said first transistor becomes conducting whenthe voltage level in said predetermined time delay voltage storage meansexceeds the reference voltage level in said reference voltage controlmeans, said second transistor is rendered conducting upon thecommencement of conduction of said first transistor, (7) a bypass meansfor said solid state relay energization control means and said referencevoltage control means,

1 1 said bypass means electrically connectedto said direct currentvoltage source and controlled by said relay to provide a bypass circuitto maintain said relay energized, simultaneously with the conduction ofsaid rst and second transistors said time delay voltage 'storage meansrdelivers its stored voltage energy through said transistors to energizesaid relay and' said reference voltage is brought to zero by thecompletion of said bypass circuit through said bypass means to saidrelay, whereby said relay is quickly picked up and maintained picked upby the combined action of said storage voltage in said predeterminedtime delay voltage storage means and said circuit through said bypassmeans.

11; The fail-safe solid state time element relay of claim 10 whereinsaid solid state relay energization control means includes an excessvoltage drainoif means electrically connected to said predetermined timedeay storage means.

12. The fail-safe solid state time element relay of claim 11 whereinsaid predetermined time delay storage means includes a series circuitwhich includes a variable resistance, a xed resistance and a multiplecapacitor means;

said multiple capacitor means charges gradually through said variableresistance and said fixed resistance which respectively provide a timeadjustment function and a minimum time adjustment for said time elementrelay.

13. The fail-safe solid state time element relay of claim 12 whereinsaid multiple capacitor means includes a plurality of capacitorselectrically connected in parallel,

each capacitor having a pair of leads, said plurality of electricallyconnected parallel capacitors having an additional parallel pair ofelectrical connections across all of said capacitor leads, one

of said pair of additional electrical connections positioned on eitherside of said plurality of capacitors and in electrical contact with saidpairs of electrical leads to thereby provide a fail-safe capacitorarrange ment immune from the effects of possible failure of saidparallel electrical connection.

14. The fail-safe solid state time element relay of claim 13 whereinsaid safety voltage storage means includes a capacitor which storesenough energy to prevent early triggering due to loss of said referencevoltage during any momentary interruption of input power from saiddirect current voltage source or the appearance in the direct currentvoltage source of an externally induced signal of negative nature. 1

15. The fail-safe solid state time element relay of claim 14 whereinsaid excess voltage drainol means includes a resistive element having aresistive value which is less than the total resistive value of saidreference voltage control means, said excess voltage drainoi meansthereby providing a rapid drainoff of residual charges on said multiplecapacitor means whether 0r not said solid state relay energization meansis triggered into conduction.

16. The fail-safe solid state time element relay of claim 12 whereinsaid relay includes transient signal suppression means to prevent relayenergizing current from bypassing the coil of said relay andsimultaneously preventing early energization of said relay due toexternally induced transient voltage signals which would momentarilyincrease the voltage at said multiple capacitor means which wouldproduce an early triggering of said solid state relay energizationmeans.

17. The fail-safe soli-d state time element relay of claim 16 whereinsaid transient signal suppression means also prevents early energizationof said relay due to externally induced transient voltage signals whichwould momentarily reduce said reference voltage in said referencevoltage means which would produce an early triggering of said solidstate relay energization means.

18. The fail-safe solid state time element relayof claim 17 which.includes a voltage limiting means electrically connected to said directcurrent voltage source and said predetermined time delay storage means,

said voltage limiting means clipping off excess voltage transients whichmay be impressed upon the direct current voltage source.

References Cited UNITED STATES PATENTS 3,038,106 6/1962 Cutsogeorge etal. 317-1485 3,069,552 12/1962 Thomson 250--214 3,082,329 3/1963 Meyeret al. 307-885 3,287,608 11/1966 Pokrant 317-142 3,295,424 1/1967 Biber95-10 LEE T. HIX, Primary Examiner. I. A. SILVERMAN, Assistant Examiner.l

1. A FAIL-SAFE SOLID STATE TIME ELEMENT RELAY WHICH IS IMMUNE TO RELAYPICKUP DUE TO EARLY TRIGGERING, SAID TIME DELAY RELAY CAPABLE OFADJUSTABLE TIME INTERVALS FOLLOWED BY QUICK RELAY PICKUP AT THE END OFSAID TIME INTERVALS, SAID TIME ELEMENT RELAY HAVING IN COMBINATION: (1)AN EXTERNALLY CONTROLLED DIRECT CURRENT VOLTAGE SOURCE, (2) SOLID STATERELAY ENERGIZATION CONTROL MEANS, (3) A PREDETERMINED TIME RELAY VOLTAGESTORAGE MEANS ELECTRICALLY CONNECTED TO SAID SOLID STATE RELAYENERGIZATION CONTROL MEANS, (4) A SAFETY VOLTAGE STORAGE MEANSELECTRICALLY CONNECTED BETWEEN SAID DIRECT CURRENT VOLTAGE SOURCE ANDSAID PREDETERMINED TIME DELAY VOLTAGE STORAGE MEANS, SAID VOLTAGESTORAGE MEANS SOTRING ENERGY FROM SAID DIRECT CURRENT VOLTAGE SOURCE TOTHEREBY PROVIDE A STANDBY REFERENCE VOLTAGE TO SAID SOLID STATE RELAYENERGIZATION CONTROL MEANS. (5) AN EXCESS VOLTAGE DRAINOFF MEANS FORSAID PREDETERMINED TIME DELAY VOLTAGE STORAGE MEANS ELECTRICALLYCONNECTED TO SAID PREDETERMINED TIME DELAY VOLTAGE STORAGE MEANS, (6)REFERENCE VOLTAGE CONTROL MEANS ELECTRICALLY CONNECTED TO SAID SOLIDSTATE RELAY ENERGIZATION CONTROL MEANS. (7) A RELAY ELECTRICALLYCONNECTED TO SAID SOLID STATE RELAY ENERGIZATION CONTROL MEANS, (8) ABYPASS MEANS FOR SAID SOLID STATE RELAY ENERGIZATION CONTROL MEANS ANDSAID REFERENCE VOLTAGE CONTROL MEANS, SAID BYPASS MEANS ELECTRICALLYCONNECTED TO SAID DIRECT CURRENT VOLTAGE SOURCE AND CONTROLLED BY SAIDRELAY TO PROVIDE A BYPASS CIRCUIT TO MAINTAIN SAID RELAY ENERGIZED.